1. Field of the Invention
The present invention generally relates to the design of integrated circuits, and more particularly to a method of simulating the operation of an integrated circuit design which has a plurality of signal storage elements such as latches.
2. Description of the Related Art
Integrated circuits are used for a wide variety of electronic applications, from simple devices such as wristwatches, to the most complex computer systems. A microelectronic integrated circuit (IC) chip can generally be thought of as a collection of logic cells with electrical interconnections between the cells, formed on a semiconductor substrate (e.g., silicon). An IC may include a very large number of cells and require complicated connections between the cells. A cell is a group of one or more circuit elements such as transistors, capacitors, resistors, inductors, and other basic circuit elements grouped to perform a logic function. Cell types include, for example, core cells, scan cells and input/output (I/O) cells. Each of the cells of an IC may have one or more pins, each of which in turn may be connected to one or more other pins of the IC by wires. The wires connecting the pins of the IC are also formed on the surface of the chip. For more complex designs, there are typically at least four distinct layers of conducting media available for routing, such as a polysilicon layer and three metal layers (metal-1, metal-2, and metal-3). The polysilicon layer, metal-1, metal-2, and metal-3 are all used for vertical and/or horizontal routing.
An IC chip is fabricated by first conceiving the logical circuit description, and then converting that logical description into a physical description, or geometric layout. This process is usually carried out using a “netlist,” which is a record of all of the nets, or interconnections, between the cell pins. A layout typically consists of a set of planar geometric shapes in several layers. The layout is then checked to ensure that it meets all of the design requirements, particularly timing requirements. The result is a set of design files known as an intermediate form that describes the layout. The design files are then converted into pattern generator files that are used to produce patterns called masks by an optical or electron beam pattern generator. During fabrication, these masks are used to pattern a silicon wafer using a sequence of photolithographic steps. The process of converting the specifications of an electrical circuit into a layout is called the physical design.
Due to the large number of components and the details required by the fabrication process for very large scale integrated (VLSI) devices, physical design is not practical without the aid of computers. As a result, most phases of physical design extensively use computer-aided design (CAD) tools, and many phases have already been partially or fully automated. Automation of the physical design process has increased the level of integration, reduced turn around time and enhanced chip performance. Several different programming languages have been created for electronic design automation (EDA), including Verilog, VHDL and TDML. A typical EDA system receives one or more high level behavioral descriptions of an IC device, and translates this high level design language description into netlists of various levels of abstraction.
Physical synthesis is prominent in the automated design of integrated circuits such as high performance processors and application specific integrated circuits (ASICs). Physical synthesis is the process of concurrently optimizing placement, timing, power consumption, crosstalk effects and the like in an integrated circuit design using various simulation and analysis tools. This comprehensive approach helps to eliminate iterations between circuit analysis and place-and-route. Physical synthesis has the ability to repower gates (changing their sizes), insert repeaters (buffers or inverters), clone gates or other combinational logic, etc., so the area of logic in the design remains fluid.
Faster performance and predictability of responses are elements of interest in circuit designs. As process technology scales to the deep-submicron (DSM) regime, it becomes more difficult to accurately model circuit performance, particularly regarding unknown behaviors of circuit components. One situation that may lead to unknown behaviors relates to the initialized states of latches in a circuit design. A binary latch captures an input data signal (“0” or “1”) each time a clock control is activated, and passes the captured value to its output. However, at circuit reset during the simulation the latches have not captured any particular value and so have an indeterminate binary state, represented in some conventional circuit simulators as an “X” value.
This situation is not a problem in behavioral register transfer level (RTL) simulation, but can create difficulties in gate-level netlist simulation depending on how the synthesis tool implements the synchronous reset function. While both the behavioral RTL and the gate-level netlist are logically equivalent, their simulation behaviors differ. This difference may be illustrated using the following two Verilog expressions for latch assignment with a standard edge-triggered data flip-flop:RegA<=(RegA+Reset)′,   (1)RegA<=(RegA+(RegA)′(Reset))′  (2)In the first expression (RTL), register A is assigned the complementary value of the logical OR combination of the existing value in register A and the reset value. In the second expression (gate-level netlist of the same latch), register A is assigned the complementary value of the logical OR combination of the existing value in register A and the logical AND combination of the complement of the existing value in register A and the reset value. Application of DeMorgan's Theorem shows that both of these expressions are logically equivalent; however, the simulation behavior is different when a reset is applied. When the simulator is first started, all registers in the design are un-initialized and therefore are at an “X” state. In the first expression, the assertion (logic “1”) of “Reset” when “RegA” is at its un-initialized state will result in a transition of “RegA” to a logic “0” independent of the existing state of “RegA”, i.e., the expression translates to RegA<=(X+1)′, and a logic “1” ORed with anything will always produce a logic “1”. In the second expression, the assertion (logic “1”) of “Reset” when “RegA” is at its un-initialized state will result in “RegA” remaining indeterminate, i.e., the expression translates to RegA<=(X+X′(1))′, and a logic “1” ANDed with an “X” will always produce an “X” since the resultant value is dependent upon the state of “X”.
These “X” values can propagate throughout the circuit design during gate-level netlist simulation, as illustrated by the flow chart of FIG. 1 which shows a typical simulation process. The process begins when the simulation tool receives the circuit description or netlist (1). The circuit design is loaded into the simulator (2) and a reset phase begins its first cycle (3). There are one or more additional clock cycles during the reset phase (4), and the reset signal is then released (5). Any indeterminate “X” values then propagate during simulation of circuit operation to the extent allowed by the simulator (6). The ending results (states of the various circuit components) are stored for further analysis and processing (7). The simulation may not, however, be completed to the point desired due to the “X” propagation. Since registers may remain in an indeterminate state despite the application of a synchronous reset executed by the simulation tool, the simulation is unable to progress when specific values become necessary as inputs to downstream circuit components.
Circuit designers continually search for efficient techniques to accurately characterize these unknown behaviors. One known solution is to pass certain flags to the synthesis tool that causes the reset circuitry to be mapped in a manner that does not cause the outputs of the latches to be un-initialized after the assertion of a reset. The drawback of this approach is that choosing and setting these flags requires an highly experienced designer and intricate knowledge of the synthesis tool, which differs from vendor to vendor. Moreover, the resulting gate-level implementation after applying these flags has been shown to be inconsistent from design to design, thus requiring several synthesis iterations to produce a netlist that simulates correctly. Computational requirements are significantly increasing with the ever larger numbers of latches present in modern integrated circuit designs. These iterations should be unnecessary if the behavioral RTL and gate-level netlist are logically equivalent. It would, therefore, be desirable to devise an improved method of circuit simulation which can proceed without requiring a re-synthesis of the original RTL of the design. It would be further advantageous if the method could easily be implemented to enhance existing design tools.